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| CXG1091TN SP4T GSM Dualband Antenna Switch 5V + Logic Description The SP4T + logic is a high power antenna switch MMIC for use in dualband GSM handsets. One Antenna can be routed to either of the 2 Tx or 2 Rx ports. It operates from 3 CMOS control lines (Tx ON/OFF and GSM900/1800 and Standby). The Sony's J-FET process is used for low insertion loss. Features * 3 CMOS compatible control lines * 34dBm power handling at 5.0V (GSM900) * Low second harmonic < - 30dBm at 34dBm * Small package size: 16-pin TSSOP (3.9 x 4.1mm) Applications Dualband handsets using combinations of GSM900/GSM1800/GSM1900 and DECT Structure GaAs J-FET MMIC Truth Table On Pass Ant.-Tx1 GSM900 Ant.-Tx2 GSM1800 Ant.-Rx1 GSM900/1800 Ant.-Rx2 GSM900/1800 OFF Band select H L L H -- Tx (H)/Rx (L) H H L L -- Standby H H H H L 16 pin TSSOP (Plastic) Absolute Maximum Ratings (Ta = 25C) 7 * Bias voltage VDD * Control voltage Vctl 5 * Operating temperature Topr -35 to +85 * Storage temperature Tstg -65 to +150 V V C C GaAs MMICs are ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E99758A9Y-PS CXG1091TN Electrical Characteristics Item Symbol Port Ant-Tx1, Tx2 Insertion loss IL Ant-Rx1, Rx2 Condition 1 2 3 4 1 Ant-Tx1, Tx2 Isolation ISO. Ant-Rx1, Rx2 VSWR Harmonics Note) P1dB compression input power Switching speed Control current Supply current Leakage current 1 2 3 4 VSWR 2fo 3fo P1dB TSW ICTL IDD IIK STBY = H STBY = L 1, 2 Ant-Tx1, Tx2 Ant-Tx1, Tx2 1, 2 1, 2 36 1 100 0.5 2 3 4 20 17 24 20 Min. Typ. 0.5 0.6 0.55 0.7 25 20 28 24 1.2 (Ta = 25C) Max. 0.75 0.85 0.75 0.9 Unit dB dB dB dB dB dB dB dB -30 -30 dBm dBm dBm s A 1 50 mA A Pin = 34dBm, 880 to 915MHz, VDD = 5.0V Pin = 32dBm, 1710 to 1785MHz, VDD = 5.0V Pin = 10dBm, 925 to 960MHz Pin = 10dBm, 1805 to 1880MHz Note) Harmonics measured with Tx inputs harmonically matched. CMOS Logic Values Logic High Low Min. 2.4V Typ. 3.0V 0.0V (Ta = 25C) Max. 0.8V -2- CXG1091TN Recommended Circuit 100pF 9 GND Tx1 8 10 GND 100pF 11 ANT GND 7 100pF Tx2 6 ( RRF ) GND 5 100pF Rx1 4 12 GND 13 VDD 100pF 14 GND GND 3 100pF 15 Band Select 100pF 16 Tx/Rx 100pF Rx2 2 STDBY 1 100pF PCB Layout Recommendations * As indicated in the diagram AC coupling capacitors are necessary to the Ant, Tx1, Tx2, Rx1, Rx2 pins. * Ground plane should be included under the device and all ground pins connected to this. * RRF (68k) is used to be stabilized the electrical characteristics at high power signal input. -3- CXG1091TN Package Outline Unit: mm 16PIN TSSOP(PLASTIC) 1.2MAX 4.1 2.05 A 16 X S B 9 X2 0.2 SAB 0.08 S 0.1 (3.0) 0.1 0.05 0.25 2.9 0.1 X 0.5 0.1 SA B 0 to 8 0.08 M S A B 0.2 0.02 + 0.036 0.22 - 0.03 DETAIL B PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE TSSOP-16P-L01 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.03g -4- 0.1 0.01 + 0.026 0.12 - 0.02 0.45 0.1 1 8 X4 3.9 |
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